D to A Converter


Problem

This project was an assignment from my Circuit II class (EECE 356). The assignment was given as follows:

design 1

Design a D/A converter with the following required characteristics:

  • Vout ranges from +10V to -10V (continuous range analog signal)
  • Vout = +10V when digital register content = "00000000"
  • Vout = -10V when digital register content = "11111111"
  • Vout = 0V when digital register content = "10000000"

You are allowed to use only inverting summing op-amps and/or regular inverting op-amp circuits. Provide complete design including circuit diagram showing all stages, resistors, equations and calculations. Graph input data and varying analog input.



Design

This converter will have to take the digital word that is given by the parallel digital register and create an analog voltage level corresponding to that digital 8 bit word. Arbitrarily, the design of the converter will look something like:


design 2

The specifications require that the word "00000000" = 10V, "10000000" = 0V, and "11111111" = -10V. We can use these three voltage levels to adjust our resistance values accordingly.



Choosing Resistance Values

The resistance values of each input will have to be different, as each bit does not carry the same significance. Since we know that the output voltage of the inverting summing op-amp conforms to the equation:


design 8

We can see that the more significant the bit (such as b7) the less the resistance value for that input will have to be. This allows the more significant bits to have a larger effect on the output than the less significant bits.

We will arbitrarily choose our first resistor value to be 500 ohms and double the resistance value of each resistor as we go down from b7 since the significance of each input is only half of the one preceding it. This gives us the following values:


  • R7 = 500 ohms
  • R6 = 1k ohms
  • R5 = 2k ohms
  • R4 = 4k ohms
  • R3 = 8k ohms
  • R2 = 16k ohms
  • R1 = 32k ohms
  • R0 = 64k ohms
  • RB = ? (Bias Resistance)
  • VB = ? (Bias Voltage Level)
  • RF = 1k ohms (Feedback resistance)



Solving for RB (Bias Resistance) and VB (Bias Voltage)

To effectively shift the output, we will need to bias the output with a bias input with a constant voltage and solve for its resistance value. From the equation, when all of the inputs are 0, the only voltage level will be the bias input:


design 9

Since the requirement is for all zeros to give a voltage of +10V, it will be convenient to make this voltage (VB) equal to -10V and the resistor ratio equal to 1 so that when no other voltages are present, a +10V voltage appears on the output.

To get a resistor ratio = 1, RB will have to equal RF (1k ohms). However, we can double check this value by solving for RB when all of the inputs are 1:


design 10

Solving this for RB, we get RB = 1008 ohms. We can round this value to 1k ohms for practical and laboratory purposes



Testing Our Values

Now that we have chosen our values and calculated RB, we can now test them. Since we have forced the "00000000" bit word to be +10V, we need not examine it. Also, we have chosen a value for RB so that the input of "11111111" will yield an output of -10V. The only case left is the one in the middle. The bit word "10000000" should yield an output of 0V. Plugging in our values:


design 11

Now that our values seem to be correct, we can finish our design and figure out how to generate this -10V voltage level within the restraints of the design specification.



Putting the Design Together

Generating -10V

Since we have a -15V input and a 5V input, it would be easy to implement a difference amplifier and setting the resistances equal to each other so it performs a simple subtraction. However, since we are not allowed the difference amplifier in our design, we must find another solution.

Using a summing amplifier, we can adjust the voltage ratios between RF and each of the resistors to create ratios of 1/3 and 3. We can then use these ratios with the -15V and +5V voltages to create -5V and +15V terms. The summing amplifier will add the terms and invert them producing a -10V level. This could also be done by simply inverting each input first with 2 inverting op-amps and then using a third to sum them, but requires more hardware, power consumption, and complexity. Implementing this design would give us:


design 3

Letting R1 = 90k, R2 = 10k, and RF = 30k :


design 12

Using this with the previous design and values, we can now implement the design and test.



Testing

The result of our design is as follows with the resistor values from above:


design 4

The following inputs produce the following outputs with the design pictured above:


Digital Input word Analog Output Voltage
00000000+ 10.00 V
00010000+ 8.75 V
00100000+ 7.50 V
00110000+ 6.25 V
01000000+ 5.00 V
01010000+ 3.75 V
01100000+ 2.50 V
01110000+ 1.25 V
100000000.00 V
10010000- 1.25 V
10100000- 2.50 V
10110000- 3.75 V
11000000- 5.00 V
11010000- 6.25 V
11100000- 7.50 V
11110000- 8.75 V


Obviously this is only a subset of the input values. Taking in all of the values and plotting them against the analog output we get:


design 6

If we continue to count up and down, we will see the analog output vary accordingly:


design 7



Possible Improvements

One possible improvement that could be made is adding one inverting op-amp to give the user access to the same exact output but inverted. Both outputs could be available. On the inverted output, the digital word "11111111" would now produce +10V and the "00000000" input would produce the -10V output. This could be done by:


design 5

Now that our values seem to be correct, we can finish our design and figure out how to generate this -10V voltage level within the restraints of the design specification.



PSPICE Analysis

This analysis was done after the design. Looking back, I can see that we changed the resistor values. I am not sure why we did, but what is important is that their relative relationship is the same.

Three runs were done. The inputs were "00000000", "11111111", and "10000000" repsectively.

Run 1:


design 13

Run 2:


design 14

Run 3:


design 15


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